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HD74HC112 Dual J-K Flip-Flops (with Preset and Clear) REJ03D0562-0200 (Previous ADE-205-435) Rev.2.00 Oct 11, 2005 Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic level on the corresponding input. Features * * * * * * High Speed Operation: tpd (Clock to Q) = 17 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 2 A max (Ta = 25C) Ordering Information Part Name HD74HC112P HD74HC112FPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Abbreviation P -- EL (2,000 pcs/reel) Taping Abbreviation (Quantity) PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability. Function Table Inputs Preset L H L H H H H H H H Clear H L L H H H H H H H L H Clock X X X J X X X L L H H X X X K X X X L H L H X X X L H Toggle No change No change No change Q H L H *1 Outputs Q L H H No change H L *1 H: High level L: Low level X: Irrelevant Note: 1. Q and Q will remain High as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and Clear go High simultaneously. Rev.2.00, Oct 11, 2005 page 1 of 6 HD74HC112 Pin Arrangement 1CK 1K 1J 1PR 1Q 1Q 2Q GND 1 2 3 4 5 6 7 8 (Top view) K CK J CLR PR Q Q J CK K PR CLR Q Q 13 2CK 12 2K 11 2J 10 2PR 9 2Q 16 Vcc 15 1CLR 14 2CLR Logic Diagram (1/2) PR CLR J K CK CK CK CK CK CK Q Q CK CK CK CK CK Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Symbol VCC Vin, Vout IIK, IOK IO ICC or IGND PT Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 25 50 500 Unit V V mA mA mA mW Storage temperature Tstg -65 to +150 C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.2.00, Oct 11, 2005 page 2 of 6 HD74HC112 Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time Note: *1 Symbol VCC VIN, VOUT Ta tr , tf Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400 Unit V V C Conditions VCC = 2.0 V ns VCC = 4.5 V VCC = 6.0 V 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Ta = 25C Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Typ -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- Max -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 2.0 Ta = -40 to+85C Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- Max -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 20 Unit V Test Conditions VIL V Output voltage VOH V Vin = VIH or VIL IOH = -20 A VOL V Vin = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 A IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A Input current Quiescent supply current Iin ICC Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Min -- -- -- -- -- -- -- -- -- -- -- -- Ta = 25C Ta = -40 to +85C Unit Typ Max Min Max -- -- -- -- 17 -- -- 15 -- -- 16 -- 6 30 35 150 30 26 140 28 24 140 28 24 -- -- -- -- -- -- -- -- -- -- -- -- 5 24 28 190 38 33 175 35 30 175 35 30 MHz Test Conditions tPLH, tPHL ns Clock to Q or Q ns Clear to Q or Q ns Preset to Q or Q Rev.2.00, Oct 11, 2005 page 3 of 6 HD74HC112 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = 25C Item Pulse width Symbol VCC (V) tw 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Min 80 16 14 100 20 17 5 5 5 100 20 17 -- -- -- -- Typ -- 9 -- -- 3 -- -- -2 -- -- 2 -- -- 5 -- 5 Max -- -- -- -- -- -- -- -- -- -- -- -- 75 15 13 10 Ta = -40 to +85C Min 100 20 17 125 25 21 5 5 5 125 25 21 -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- 95 19 16 10 Unit ns Test Conditions Clear, Clock Setup time tsu ns J or K to Clock Hold time th ns Clock to J or K Removal time trem ns Clear to Clock Output rise/fall time Input capacitance tTLH, tTHL ns Cin pF Test Circuit VCC VCC Output See Function Table Input Pulse generator Zout = 50 Input Pulse generator Zout = 50 Preset Clock J K Clear Q CL = 50 pF Q CL = 50 pF Output Note: C L includes the probe and jig capacitance. Rev.2.00, Oct 11, 2005 page 4 of 6 HD74HC112 Waveforms * Waveform - 1 tr 90 % tf t w (L) VCC 50 % 10 % 50 % Clock 10 % 50 % 50 % t w (H) 0V t THL 90 % 50 % 10 % t TLH 90 % 50 % 10 % VOH VOL Q t PLH t PHL Q t PHL t PLH 90 % 50 % 10 % 50 % 10 % VOH VOL t THL t TLH * Waveform - 2 tf 90 % 50 % 10 % t w(clear) 90 % 50 % t PHL 90 % 50 % 10 % t PLH Q t THL 90 % 50 % 10 % t TLH Notes: 1. Input waveform: PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. The output are measured one at a time with one transition per measurement. 50 % VOL t PHL VOH 10 % t w(preset) t PLH Q 50 % VOL tr 90 % 50 % 10 % tf tr 90 % 50 % VCC 0V VCC 0V Clear Preset VOH Rev.2.00, Oct 11, 2005 page 5 of 6 HD74HC112 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g D 16 9 1 0.89 b3 8 Z E A1 A Reference Symbol Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max e D E 1 L A A1 e bp e1 b c b c p 3 e Z ( Ni/Pd/Au plating ) L JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B Previous Code FP-16DAV MASS[Typ.] 0.24g *1 D F 9 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp HE E Index mark Reference Symbol *2 c Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5 Terminal cross section ( Ni/Pd/Au plating ) 1 Z e *3 D E A2 8 bp x M L1 A1 A bp b1 c 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 1 0.20 0.25 A c HE 0 7.50 7.80 1.27 8 8.00 A1 y L e x y 0.12 0.15 0.80 0.50 1 Detail F Z L L 0.70 1.15 0.90 Rev.2.00, Oct 11, 2005 page 6 of 6 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. 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